IBM Power6 Processor Seminar Report


IBM Power6 Processor Seminar Abstract

Power6 is a processor introduced by IBM in 2007. It is a dual-core processor which implements the 64-bit IBM Power Architecture technology. An insight into the architecture of the processor will be given. The cache memory, cache controller , high frequency core, SMT implementation will be briefly elaborated. Comparision of the POWER6 with its previous version Power5 and the physical design methodology of the processor will be discussed in the report In basic terms, Power6 processor has advanced from Power5 processor in high-frequency core, larger amount of memory, more memory controllers, higher performance, high throughput, mimimised cost and circuitry, the pipeline technology and more I/O controllers. The impact of the microarchitecture on performance, power, system organization and cost will be discussed. The next- generation microprocessor is used in UNIX and Linux systems. It offers double the performance of its predecessor without much power dissipation. In design methodology, fabrication technology, clock design will be discussed. The IBM Power6 processor supports advanced dynamic power management solutions for managing not just the chip, but the entire server. The design facilitates a programmable power management solution for greater flexibility and integration into system and data-centre-wide management solutions. The processor includes a high degree of detection of soft and hard errors. Thus, an insight into the Power6 processor will be presented at the seminar. An application of the POWER6 processor also will be discussed.

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