IEEE 2011 VLSI Project Topics


WirelessCommunication

  • An improved three-factor authentication scheme using smart card with biometric privacy protection
  • The Ship Monitoring and Control Network System Design
  • Autonomous Navigation for an Unmanned Mobile Robot in Urban Areas
  • A Generic Framework for Three-Factor Authentication: Preserving Security and Privacy in Distributed Systems
  • A Low-Cost GPS&INS Integrated System Based on a FPGA Platform
  • An embedded high sensitivity navigation receiver for GPS
  • Hardware Efficiency Comparison of AES Implementations Efficient Design and Implementation of FFT

Low Power Design

  • Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
  • Design of Sequential Elements for Low Power Clocking System
  • Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design
  • Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits
  • Parameterized FPGA-Based Architecture For Parallel 1-D Filtering Algorithms
  • A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors
  • Low Power Single Bitline 6T SRAM Cell With High Read Stability
  • Low Power Subthreshold D Flip Flop
  • Low Leakage Power SRAM Cell for Embedded Memory
  • A Novel Low-Leakage 8T Differential SRAM Cell
  • Adiabatic Technique for Energy Efficient Logic Circuits Design
  • A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design
  • Performance Analysis of Power Gating designs in Low Power VLSI Circuits
  • Low-Power and Area-Efficient Carry Select Adder

Security Based

  • Improving ATM Security Via Face Recognition
  • Design of Vehicle Positioning System Based on FPGA
  • A Novel Area-Throughput Optimized Architecture for the AES Algorithm
  • Thwarting Control-Channel Jamming Attacks from Inside Jammers
  • Operation Improvement of Indoor Robot by Gesture Recognition

Image Processing

  • Image Processing in Dynamic Reconfigurable Platform
  • Real-Time Object Tracking System on FPGAs
  • Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT
  • A Universal Background Subtraction Algorithm for Video Sequences
  • A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform
  • Power Efficient Motion Estimation Algorithm and Architecture Based on Pixel Truncation
  • Architectural Implementation of High Speed Optical Flow Computation Based on Lucas- Kanade Algorithm
  • Discrete Wavelet Transform-Based Satellite Image Resolution Enhancement
  • An Efficient Denoising Architecture for Removal of Impulse Noise in Images
  • Dynamic Hand Gesture Recognition for Human- Computer Interactions
  • Dynamic Power Estimation for Motion Estimation Hardware
  • Realization of a LSB Information Hiding algorithm Based on Lifting Wavelet Transform Image
  • Blind Image Watermarking Using a Sample Projection Approach
  • A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware
  • An improved method of image edge detection based on wavelet transform
  • Mathematical Morphological Edge Detection For Remote Sensing Images
  • A New Adaptive Weight Algorithm for Salt and Pepper Noise Removal

Leave a Reply

Your email address will not be published. Required fields are marked *