System Generator & Signal Processing

  • Real Time Hardware Co-simulation of Edge Detection for Video Processing System
  • BPSK System on Spartan 3E FPGA
  • Implementation of PSK and QAM demodulators on FPGA
  • Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation
  • Platform-Independent Customizable UART Soft-Core
  • VLSI Architecture of Arithmetic Coder Used in SPIHT
  • Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
  • (Low Power Design) PSVLS 8
  • Single Phase Clocked Quasi Static Adiabatic Tree Adder
  • Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep Submicron Circuits
  • Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
  • Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks
  • Design of Low Voltage Low Power Operational Amplifier
  • Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits

Cryptography & Communication

  • A Novel Architecture for VLSI Implementation of RSA Cryptosystem
  • FPGA Hardware of the LSB Steganography Method
  • A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
  • An efficient FPGA implementation of the Advanced Encryption Standard algorithm
  • A Novel Data Embedding Method Using Adaptive Pixel Pair Matching
  • VHDL Implementation of a Flexible and Synthesizable FFT Processor

Soft Core Processor Design

  • An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion
  • Medical Image Fusion Based on Redundancy DWT and Mamdani Type Min-sum Mean-ofmax Techniques with Quantitative Analysis
  • Edge Detection of Angiogram Images Using the Classical Image Processing Techniques
  • Input/Output Peripheral Devices Control through Serial Communication using Microblaze Processor
  • Variable Scaling Factor based Invisible Image Watermarking using Hybrid DWT – SVD Compression - Decompression Technique
  • A Level Set Based Deformable Model for Segmenting Tumors in Medical Images
  • Adaptive Steganalysis of Least Significant Bit Replacement in Grayscale Natural Images
  • Analysis of CT and MRI Image Fusion using Wavelet Transform

Soft Core Processor Design

  • Design of Modified Low Power Booth Multiplier
  • An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
  • Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications Applications
  • Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
  • A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT
  • Background Subtraction Algorithm for Moving Object Detection in FPGA
  • Design and Implementation of the Discrete Wavelet Transform on an FPGA Platform to Process Data Sets of up to Three Dimensions
  • Gesture Recognition Using Field Programmable Gate Arrays Median Filter on FPGAs
  • An Autoadaptive Edge-Detection Algorithm for Flame and Fire Image Processing
  • An Efficient Denoising Architecture for Removal of Impulse Noise in Images
  • Real Time Smart Car Lock Security System Using Face Detection and Recognition

Security & System Generator

  • Implementation of a Home Automation System through a Central FPGA Controller
  • Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE
  • New Clock Generation Techniques for Synchronous Sampling of 16-QAM RF Signals 
  • QPSK Modulator on FPGA
  • Implementation of a QPSK System on FPGA
  • Models Simulation based on HDL-Simulink Platform
  • Simulation and Implementation of a BPSK Modulator on FPGA


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